Efficient OS scheduling for performance

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The paper proposes an AMPS OS that ensures fairness, stableperformance, and repeatability as well demonstrate the existing bodyof literature on thread migration and OS scheduling. Given thechallenges presented by multi-core processors, Li, Baumberger,Koufaty and Hahn (n.d) suggest the use of AMPS as an operating systemscheduler because of the following reasons:-.

  • The scheduler supports both SMP and NUMA-style performance asymmetric architectures.

  • In order to support multi-core architecture, an operating system must be able to make scheduling decisions.

  • AMPS contains 3 components which makes it an efficient OS scheduler which are asymmetry-aware load balancing, faster-core-first scheduling and NUMA aware migration.

While scheduling for performance, the researchers focus on designinga general-purpose scheduler, which enables good performance for mostapplications. The design of the AMPS model is based on thedistributed model. While schedulers for the most existingmultiprocessor operating systems use a distributed run-queue model,the distributed model achieves higher stability. Additionally, AMPSis designed to maintain the load on each core proportional to itscomputing power. Faster core scheduling is considered for the designof the AMPS, because it allows threads to run on cores that are morepowerful when they are under-utilized. The final consideration fordesign is NUMA aware migration. This is means AMPS is a schedulerthat is capable of understanding migration overhead, predictingmigration overhead and running thread migration policies.

So far, AMPS has been implemented in the Linux 2.6.16 kernel. Toemulate future multicore processors, an SMP system has been used withfour dual-core Intel processors, among a number other multicoreprocessors. In order to evaluate the performance of the scheduler,three fourths of the total cores were modulated to run at 50% oftheir full duty cycles, making their frequencies 50% lower than theother cores. The results were that AMPS improves performance,fairness and repeatability.

On the other hand, discourse reveals that researchers have conductednumerous studies on OS scheduling and the effectiveness employed inpresenting a unique and suitable framework. In fact, the paperreveals that

  • Performance-asymmetric constructions yield higher performances than cost-equivalent homogenous designs

  • Unlike previous studies, which have focused on page migration, the focus of the paper on thread migration reveals the utilization of threads’ memory to yield higher accuracy

  • Furthermore, the paper focus on several contexts that relate to AMPS design and OS scheduling such as design space, asymmetry-aware load balancing, faster core scheduling, and thread migration.

Taking into consideration the attributes discussedthroughout the paper, it is suitable to report that the authors haveprovided an efficient scheduler i.e. AMPS OS, which can sufficientlymanage both NUMA and SMP asymmetric architectures. In fact, based onexisting schedulers, the authors propose an AMPS OS that has adistributed model to achieve high yield and scalability. In fact, theproposed OS achieves a maximum speedup of 1.44 and a median of 1.16,which shows that despite the high ingenuity of AMPS OS, it does notincrease performance noticeably. However, the OS improvesrepeatability and fairness as asymmetry-aware load balancing allowsthe threads to share cores fairly. On the other hand, although theauthors differ in their assessment of conventional multiprocessorsfrom previous or current studies, they assert that an assorteddistributed multiprocessor or multi-core architecture may helpimprove fairness and performance. Categorically, the authors assertthat an exploration of the proposed scheduler design space will helpto suggest ways of extending AMPS to enhance both power consumptionand performance thus, the research reveals that AMPS OS will seegreat utilization and assessment.

References

Li, T., Baumberger, D., Koufaty, D.A &amp Hahn, S. (n.d).Efficientoperating system scheduling for performance-asymmetric multi-corearchitectures.Intel Corporation Systems Technology Lab.